Embedded SRAM memory consumes large area on today's digital electronics chips. Specifically, in microprocessors SRAM caches consume 50% of the chip area, while in Systems on Chip (SOC) consume as much as 90% of the chip area. Volatile memories require refreshing to keep information intact and this refreshing requires electrical energy which is drawn from the power supply or a battery. In mobile devices, battery life is a primary customer concern and hence the reduction of the energy required to refresh and maintain the information in SRAMs is paramount importance to many a component manufacturer. The source of information loss in a SRAM memory cell is sub-threshold and gate leakage current, which effectively drains the gate charge. Gate charge quantity represents the digital information stored in the memory. Charge leakage from the storage nodes results in loss of information. Refreshing of memory cells refers to a method of restoring the charge or significantly reducing the leakage of charge from the memory nodes.
However, as CMOS technology nodes progress, not only the number of transistors in memory chips increases, but due to shrinking transistors dimensions, leakage current per transistor increases. Clearly, the power to refresh and maintain transistor increases faster than the number of transistors on a chip. For example, each new technology node, for example, going from 90 nm to 65 nm node, increases the standby leakage seven times.
One approach to the reduction of power lost to maintaining volatile memory is dynamical suppression of leakage. In this approach, parts of the memory that are not used or idle are subjected to lower supply voltage or the voltage/ground is gated off. In lower voltage standby state, the memory cells must still maintain the information. By reducing the supply voltage, the overall power to maintain memory is reduced. This approach and analysis are shown in a number of publicly available documents including J. Wang and B. H. Calhoun titled “Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs” appearing in Solid State Circuits Technologies, ed. J. W. Swart, ISBN 978-953-307-045-2, p. 462. This chapter and references within are included in this application as a reference. Other publicly available references of these methods are published in On-Chip PT Sensor Circuits for Minimum Data Retention Voltage, book by Kyung Ki Kim in Springer-Verlag, Embedded and Multimedia Computing Technology and Service, Lecture Notes in Electrical Engineering Volume 181, 2012, pp 559-566.
The leakage-current components for a 6T SRAM cell are all supply voltage dependent and reduce with reducing supply voltage. FIG. 1 shows a circuit diagram of 6-transistor SRAM cell (PRIOR ART). The dominant components of leakage in memory cells are sub-threshold and gate leakage currents. Decreasing supply voltage (VDD) from 1 V to 0.300 V will decrease the cell leakage over 90%. Ideally, one would like to reduce the supply voltage to zero to completely eliminate the power dissipation during standby, but this not possible using this method because when the supply voltage reduces, the charge node voltage is also reduced proportionally. In the reduced supply voltage case, all transistors are off. However, the data (charge on the storage nodes) is preserved because sub-threshold leakage of PMOS load transistor is in equilibrium to NMOS pass and NMOS driver transistor leakage currents. The supply voltage has a lower limit below which the memory cell becomes unstable and is likely to lose charge from the memory nodes. This lower limit is commonly referred to as the Data Retention Voltage (DRV). Furthermore, the components of leakage current in the memory cell have different temperature dependencies. FIG. 9 shows the temperature dependence and the relative magnitude of leakage currents in a typical SRAM memory cell. Due to the difference in temperature dependence of leakage currents, a certain voltage margin is required and generally added on top of DRV. The DRV margin is temperature dependent. In temperature range from 25° C. to 125° C., the DRV margin, referred to as high-temperature DRV margin, is as low as 10 mV, because both PMOS load and NMOS driver transistor sub-threshold leakage increase equally. However, below room temperature (<25° C.), the DRV margin, referred to as the low-temperature margin, is significantly larger (˜100 mV). This higher margin is needed to maintain data integrity. The reason for this is that in the low temperature regime, the gate leakage, which is temperature independent, dominates the leakage. Sub-threshold leakage of the PMOS load transistor cannot compensate the gate leakage unless there is a larger supply voltage margin. This large margin can be realized by either lowering the threshold voltage of the PMOS load transistors or by increasing the DRV. In either case, the power dissipation of the SRAM is increased and will drain a battery of a mobile device. Approximately 60% larger dissipation power would be experienced when the margin is increased from 10 mV to 100 mV for DRV=150 mV.
Another example of a problem encountered in the placing SRAM memory to standby or sleep mode occurs in recently introduced gated-VDD or gated-GND approaches to reducing power dissipation in SRAMs. In these approaches, sections of the SRAM have their power shut off suing suitably introduced gating transistors on the power supply or in the ground. The problem with this approach is that, although it reduces the power dissipation of the cell by two orders of magnitude, it loses data: When gated-VDD method is used, the charge from the storage node maintaining the logical one is gradually drained through leakage and hence stored information lost Similarly, when gated-GND approach is implemented, the storage node maintaining the logical zero is being gradually charged though leakage.
For these reasons, there is a need in the industry for an improved method for maintaining charge on the storage nodes so that memory power in standby (sleep) mode is reduced, while the information is maintained reliably. This application discloses several methods and improved SRAM memory cell improvements that achieve improved storage maintenance under low power consumption.